This invention relates to a semiconductor memory device and, in particular, to a large-capacity random access semiconductor memory device and a method of refreshing the same.
As a semiconductor memory device, particularly, as a large-capacity random access semiconductor memory device, a dynamic random access memory (hereinafter abbreviated to DRAM) is known. The DRAM holds information as electric charges stored in capacitors of memory cells. It is therefore required to perform a refresh operation by reading the information before the electric charges fade out, amplifying the information, and restoring the information into its original state. The electric charges stored in the capacitors of the memory cells in the DRAM fade out after lapse of certain time periods which may be called information holding times or retention times. The retention times are different from cell to cell and are not constant.
The retention times are continuously distributed from a short time to a long time. This is mainly because the electric charges as “HIGH level” written in the memory cells fade out due to junction leakage. The retention times are also affected by surface leakage and relationships with adjacent cells. Accordingly, the retention times in one DRAM are long in most of the memory cells and are short in only a part of the memory cells. In existing DRAMs, in order to assure a reliable operation for all of the memory cells, a refresh cycle is determined with reference to short retention times of only a part of the memory cells. Therefore, for most of the memory cells having long retention times, the refresh operation is excessively frequently carried out. As a result, power consumption for the refresh operation is uselessly increased.
In order to save power consumption in the refresh operation, proposal is made of a method of setting a plurality of different refresh cycles for example, see Japanese Unexamined Patent Application Publication (JP-A) No. H8-306184 (corresp. to U.S. Pat. No. 5,629,898).
FIG. 1 shows a flow chart of a refresh operation according to the above-mentioned method. An adaptive refresh controller has a read-only memory (ROM) which stores refresh cycle setting information indicating short-cycle refreshing or long-cycle refreshing for each word line. In the short-cycle refreshing, the refresh operation is carried out in a reference cycle T as a short cycle. In the long-cycle refreshing, the refresh operation is carried out in a long cycle nT corresponding to n times the short cycle T. When a self-refresh mode is entered, a self-refresh operation is carried out in the long cycle nT or the short cycle T for each word line under control of the adaptive refresh controller.
When the self-refresh mode is entered, all word lines are refreshed according to addresses generated in the DRAM at first as the long-cycle refreshing in the long cycle nT. Then, after lapse of the time T corresponding to the short cycle T, the short-cycle refreshing in the short cycle T is carried out for some of the word lines. Specifically, among word lines selected by addresses generated in the DRAM, those word lines to be subjected to the long-cycle refreshing in the long cycle nT according to the refresh cycle setting information are not activated in response to an inhibit signal from the adaptive refresh controller. Thus, those word lines skip the short-cycle refreshing and are not refreshed. On the other hand, the remaining word lines to be subjected to the short-cycle refreshing in the short cycle T are refreshed. After (n−1) times repetition of the short-cycle refreshing, all word lines are refreshed again according to addresses generated in the DRAM as the long-cycle refreshing in the long cycle nT.
According to the above-mentioned process, only a part of the word lines determined to be subjected to the short-cycle refreshing are refreshed in every short cycle T while most of the word lines determined to be subjected to the long-cycle refreshing are refreshed in the long cycle nT. Thus, as compared with the case where all of the word lines are refreshed in every short cycle T, power consumption is considerably reduced.
At present, the semiconductor memory device is more and more increased in capacity. Further, the semiconductor memory device is used in a mobile terminal energized by a battery. Under the circumstances, a demand for low power consumption of the semiconductor memory device becomes more and more strict. It is therefore desired to reduce power consumption during the refresh operation specific to the DRAM. Traditionally, the retention time is measured for each word line in a production process. With reference to the result of measurement, the refresh cycle is determined as the short cycle T or the long cycle nT. The refresh time setting information indicative of the short cycle T or the long cycle nT thus determined is memorized in a PROM such as a fuse. Thus, by adaptively setting the short cycle or the long cycle as the refresh cycle, power consumption is saved.
However, the semiconductor memory device used in the mobile terminal having a small size and a thin profile is required to be further reduced in size and profile, as compared with semiconductor memory devices used in other electric apparatuses. In particular, in the semiconductor memory device used in a multi-stack package, silicon chips are reduced in thickness. In case where the silicon chips are reduced in thickness, the semiconductor memory device is susceptible to a stress during packaging or to an influence of reflowing during mounting to a printed board. If the retention times of the memory cells are varied during mounting to the printed board or during use, it is impossible to hold the data by the refresh operation in the refresh cycle according to the information preliminarily written in the PROM during production. As a result, the semiconductor memory device becomes defective.